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1. general description the PCA9537 is a 10-pin cmos device that provides 4 bits of general purpose parallel input/output (gpio) expansion with interrupt and reset for i 2 c-bus/smbus applications and was developed to enhance the nxp semiconductors family of i 2 c-bus i/o expanders. i/o expanders provide a simple solution when additional i/o is needed for acpi power switches, sensors, push-buttons, leds, fans, etc. the PCA9537 consists of a 4-bit con?guration register (input or output selection), 4-bit input port register, 4-bit output port register and a 4-bit polarity inversion register (active high or active low operation). the system master can enable the i/os as either inputs or outputs by writing to the i/o con?guration bits. the data for each input or output is kept in the corresponding input port or output port register. the polarity of the input port register can be inverted with the polarity inversion register. all registers can be read by the system master. the PCA9537 open-drain interrupt output ( int) is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. the power-on reset sets the registers to their default values and initializes the device state machine. the reset pin causes the same reset/initialization to occur without de-powering the device. the i 2 c-bus address is ?xed and allows only one device on the same i 2 c-bus/smbus. 2. features n 4-bit i 2 c-bus gpio with interrupt and reset n operating power supply voltage range of 2.3 v to 5.5 v n 5 v tolerant i/os n polarity inversion register n active low interrupt output n active low reset input n low standby current n noise ?lter on scl/sda inputs n no glitch on power-up n internal power-on reset n 4 i/o pins that default to 4 inputs n 0 hz to 400 khz clock frequency n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115 and 1000 v cdm per jesd22-c101 PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset rev. 05 7 may 2009 product data sheet
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 2 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma n offered in tssop10 package 3. ordering information 4. block diagram table 1. ordering information t amb = - 40 c to +85 c type number topside mark package name description version PCA9537dp 9537 tssop10 plastic thin shrink small outline package; 10 leads; body width 3 mm sot552-1 remark: all i/os are set to inputs at reset. fig 1. block diagram of PCA9537 PCA9537 power-on reset 002aae634 i 2 c-bus/smbus control input filter scl sda v dd input/ output ports io0 v ss 4-bit write pulse read pulse io2 io1 io3 lp filter v dd int reset
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 3 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 5. pinning information 5.1 pinning 5.2 pin description fig 2. pin con?guration for tssop10 PCA9537dp io0 v dd io1 sda io2 scl io3 int v ss reset 002aae633 1 2 3 4 5 6 8 7 10 9 table 2. pin description symbol pin description io0 1 input/output 0 io1 2 input/output 1 io2 3 input/output 2 io3 4 input/output 3 v ss 5 supply ground reset 6 active low reset input int 7 interrupt output (open-drain) scl 8 serial clock line sda 9 serial data line v dd 10 supply voltage
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 4 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 6. functional description refer to figure 1 bloc k diag r am of PCA9537 . 6.1 device address 6.2 registers 6.2.1 command byte the command byte is the ?rst byte to follow the address byte during a write transmission. it is used as a pointer to determine which of the registers will be written or read. 6.2.2 register 0 - input port register this register is a read-only port. it re?ects the incoming logic levels of the pins, regardless of whether the pin is de?ned as an input or an output by register 3. writes to this register have no effect. the default value x is determined by the externally applied logic level. fig 3. PCA9537 address r/w 002aae635 1 0 0 1 0 0 1 slave address fixed table 3. command byte command protocol function 0 read byte input port register 1 read/write byte output port register 2 read/write byte polarity inversion register 3 read/write byte con?guration register table 4. register 0 - input port register bit description legend: * default value. bit symbol access value description 7 i7 read only 1* not used 6 i6 read only 1* 5 i5 read only 1* 4 i4 read only 1* 3 i3 read only x* value x is determined by externally applied logic level 2 i2 read only x* 1 i1 read only x* 0 i0 read only x*
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 5 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 6.2.3 register 1 - output port register this register re?ects the outgoing logic levels of the pins de?ned as outputs by register 3. bit values in this register have no effect on pins de?ned as inputs. reads from this register return the value that is in the ?ip-?op controlling the output selection, not the actual pin value. 6.2.4 register 2 - polarity inversion register this register allows the user to invert the polarity of the input port register data. if a bit in this register is set (written with 1), the corresponding input port data is inverted. if a bit in this register is cleared (written with a 0), the input port data polarity is retained. table 5. register 1 - output port register bit description legend: * default value. bit symbol access value description 7 o7 r 1* not used 6o6 r 1* 5o5 r 1* 4o4 r 1* 3 o3 r 1* re?ects outgoing logic levels of pins de?ned as outputs by register 3 2o2 r 1* 1o1 r 1* 0o0 r 1* table 6. register 2 - polarity inversion register bit description legend: * default value. bit symbol access value description 7 n7 r/w 0* not used 6 n6 r/w 0* 5 n5 r/w 0* 4 n4 r/w 0* 3 n3 r/w 0* inverts polarity of input port register data 0 = input port register data retained (default value) 1 = input port register data inverted 2 n2 r/w 0* 1 n1 r/w 0* 0 n0 r/w 0*
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 6 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 6.2.5 register 3 - con?guration register this register con?gures the directions of the i/o pins. if a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. if a bit in this register is cleared, the corresponding port pin is enabled as an output. at reset, the i/os are con?gured as inputs. 6.3 power-on reset when power is applied to v dd , an internal power-on reset (por) holds the PCA9537 in a reset condition until v dd has reached v por . at that point, the reset condition is released and the PCA9537 registers and state machine will initialize to their default states. thereafter, v dd must be lowered below 0.2 v to reset the device. for a power reset cycle, v dd must be lowered below 0.2 v and then restored to the operating voltage. 6.4 reset input a reset can be accomplished by holding the reset pin low for a minimum of t w(rst) . the PCA9537 registers and smbus/i 2 c-bus state machine will be held in their default state until the reset input is once again high. this input requires a pull-up resistor to v dd if no active connection is used. 6.5 interrupt output the open-drain interrupt output ( int) is activated when one of the port pins changes state and the pin is con?gured as an input. the interrupt is de-activated when the input returns to its previous state or the input port register is read. note that changing an i/o from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register. table 7. register 3 - con?guration register bit description legend: * default value. bit symbol access value description 7 c7 r/w 1* not used 6 c6 r/w 1* 5 c5 r/w 1* 4 c4 r/w 1* 3 c3 r/w 1* con?gures the directions of the i/o pins 0 = corresponding port pin enabled as an output 1 = corresponding port pin con?gured as an input (default value) 2 c2 r/w 1* 1 c1 r/w 1* 0 c0 r/w 1*
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 7 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 6.6 i/o port when an i/o is con?gured as an input, fets q1 and q2 are off, creating a high-impedance input. the input voltage may be raised above v dd to a maximum of 5.5 v. if the i/o is con?gured as an output, then either q1 or q2 is enabled, depending on the state of the output port register. care should be exercised if an external voltage is applied to an i/o con?gured as an output because of the low-impedance paths that exist between the pin and either v dd or v ss . remark: at power-on reset, all registers return to default values. fig 4. simpli?ed schematic of io0 to io3 v dd i/o pin output port register data configuration register dq ck q data from shift register write configuration pulse output port register dq ck write pulse polarity inversion register dq ck data from shift register write polarity pulse input port register dq ck read pulse input port register data polarity inversion register data 002aad723 ff data from shift register ff ff ff q1 q2 v ss to int
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 8 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 6.7 bus transactions data is transmitted to the PCA9537 registers using the write mode as shown in figure 5 and figure 6 . data is read from the PCA9537 registers using the read mode as shown in figure 7 and figure 8 . these devices do not implement an auto-increment function so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. expanded diagram is shown in figure 16 . fig 5. write to output port register 0 a s slave address start condition r/w acknowledge from slave 002aae636 0000001 0 command byte a acknowledge from slave 12345678 scl 9 sda data 1 a write to port data out from port t v(q) acknowledge from slave data 1 valid data to port 001001 1 p stop condition fig 6. write to con?guration or polarity inversion registers 0 a s slave address start condition r/w acknowledge from slave 002aae637 0000011/0 0 command byte a acknowledge from slave 12345678 scl 9 sda data 1 a data to register acknowledge from slave data to register 001001 1 p stop condition
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 9 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset fig 7. read from register a s start condition r/w acknowledge from slave 002aae638 a acknowledge from slave sda a p acknowledge from master data (first byte) slave address stop condition s (repeated) start condition (cont.) (cont.) 0010011 a 1 r/w acknowledge from slave slave address at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter na no acknowledge from master command byte 001001 1 0 data from register data (last byte) data from register this ?gure assumes the command byte has previously been programmed with 00h. transfer of data can be stopped at any moment by a stop condition. expanded diagram is shown in figure 15 . fig 8. read input port register 0010011 a s1 slave address start condition r/w acknowledge from slave 002aae639 data from port a acknowledge from master sda 1 no acknowledge from master read from port data into port data from port data 1 data 4 int data 4 data 2 data 3 p stop condition t v(int) t rst(int) t h(d) t su(d) 12345678 scl 9 data 1
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 10 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 7. application design-in information 7.1 minimizing i dd when the i/os are used to control leds when the i/os are used to control leds, they are normally connected to v dd through a resistor as shown in figure 9 . since the led acts as a diode, when the led is off the i/o v i is about 1.2 v less than v dd . the supply current, i dd , increases as v i becomes lower than v dd . designs needing to minimize current consumption, such as battery power applications, should consider maintaining the i/o pins greater than or equal to v dd when the led is off. figure 10 shows a high value resistor in parallel with the led. figure 11 shows v dd less than the led supply voltage by at least 1.2 v. both of these methods maintain the i/o v i at or above v dd and prevents additional supply current consumption when the led is off. device address is 1001 001x for this example. io0, io2, io3 con?gured as outputs. io1 con?gured as input. fig 9. typical application PCA9537 io0 io1 scl sda v dd (5 v) master controller scl sda int io2 v dd v dd v ss int 10 k w sub-system 1 (e.g., temp sensor) io3 int sub-system 2 (e.g., counter) reset controlled switch (e.g., cbt device) a b enable v ss 002aae640 10 k w 10 k w 2 k w 100 k w reset reset 10 k w fig 10. high value resistor in parallel with the led fig 11. device supplied by a lower voltage 002aac660 led v dd ion 100 k w v dd 002aac661 led v dd ion 3.3 v 5 v
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 11 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 8. limiting values 9. static characteristics table 8. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.5 +6.0 v i i input current - 20 ma v i/o voltage on an input/output pin v ss - 0.5 5.5 v i o(ion) output current on pin ion - 50 ma i dd supply current - 85 ma i ss ground supply current - 100 ma p tot total power dissipation - 200 mw t stg storage temperature - 65 +150 c t amb ambient temperature operating - 40 +85 c t j(max) maximum junction temperature - +125 c table 9. static characteristics v dd = 2.3 v to 5.5 v; v ss =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v dd supply voltage 2.3 - 5.5 v i dd supply current operating mode; v dd = 5.5 v; no load; f scl = 100 khz - 104 175 m a i stbl low-level standby current standby mode; v dd = 5.5 v; no load; v i =v ss ; f scl = 0 khz; i/o = inputs - 0.25 1 m a i stbh high-level standby current standby mode; v dd = 5.5 v; no load; v i =v dd ; f scl = 0 khz; i/o = inputs - 0.25 1 m a v por power-on reset voltage no load; v i =v dd or v ss [1] - 1.5 1.65 v input scl; input/output sda v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd - 5.5 v i ol low-level output current v ol = 0.4 v 3 7 - ma i l leakage current v i =v dd =v ss - 1-+1 m a c i input capacitance v i =v ss - 5 10 pf
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 12 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset [1] v dd must be lowered to 0.2 v in order to reset part. [2] each i/o must be externally limited to a maximum of 25 ma and the device must be limited to a maximum current of 100 ma. [3] the total current sourced by all i/os must be limited to 85 ma. i/os v il low-level input voltage - 0.5 - +0.8 v v ih high-level input voltage 2.0 - 5.5 v i ol low-level output current v ol = 0.5 v v dd = 2.3 v [2] 810- ma v dd = 3.0 v [2] 814- ma v dd = 4.5 v [2] 817- ma v ol = 0.7 v v dd = 2.3 v [2] 10 13 - ma v dd = 3.0 v [2] 10 19 - ma v dd = 4.5 v [2] 10 24 - ma v oh high-level output voltage i oh = - 8ma v dd = 2.3 v [3] 1.8 - - v v dd = 3.0 v [3] 2.6 - - v v dd = 4.5 v [3] 4.1 - - v i oh = - 10 ma v dd = 2.3 v [3] 1.7 - - v v dd = 3.0 v [3] 2.5 - - v v dd = 4.5 v [3] 4.0 - - v i l leakage current v i =v dd =v ss - 1-+1 m a c i input capacitance - 5 10 pf interrupt int i ol low-level output current v ol = 0.4 v 3 13 - ma i oh high-level output current v ol = 0.4 v - 1-+1 m a select input reset v il low-level input voltage - 0.5 - +0.8 v v ih high-level input voltage 2.0 - 5.5 v i l leakage current v i =v dd =v ss - 1-+1 m a table 9. static characteristics continued v dd = 2.3 v to 5.5 v; v ss =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 13 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 10. dynamic characteristics [1] t vd;ack = time for acknowledgement signal from scl low to sda (out) low. [2] t vd;dat = minimum time for the sda data out to be valid following scl low. [3] c b = total capacitance of one bus line in pf. table 10. dynamic characteristics symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max f scl scl clock frequency 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - m s t hd;sta hold time (repeated) start condition 4.0 - 0.6 - m s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - m s t su;sto set-up time for stop condition 4.0 - 0.6 - m s t hd;dat data hold time 0 - 0 - ns t vd;ack data valid acknowledge time [1] 0.3 3.45 0.1 0.9 m s t vd;dat data valid time [2] 300 - 50 - ns t su;dat data set-up time 250 - 100 - ns t low low period of the scl clock 4.7 - 1.3 - m s t high high period of the scl clock 4.0 - 0.6 - m s t r rise time of both sda and scl signals - 1000 20 + 0.1c b [3] 300 ns t f fall time of both sda and scl signals - 300 20 + 0.1c b [3] 300 ns t sp pulse width of spikes that must be suppressed by the input ?lter - 50 - 50 ns port timing t v(q) data output valid time - 200 - 200 ns t su(d) data input set-up time 100 - 100 - ns t h(d) data input hold time 1 - 1 - m s interrupt timing t v(int) valid time on pin int - 4 - 4 m s t rst(int) reset time on pin int - 4 - 4 m s reset t w(rst) reset pulse width 4 - 4 - ns t rec(rst) reset recovery time 0 - 0 - ns t rst reset time 400 - 400 - ns
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 14 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset fig 12. de?nition of timing t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 rise and fall times refer to v il and v ih . fig 13. i 2 c-bus timing diagram scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 002aab285 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 1 (d1) bit 0 (d0) 1 / f scl t r t vd;dat acknowledge (a) stop condition (p) fig 14. de?nition of reset timing sda scl 002aad732 t rst 50 % 30 % 50 % 50 % 50 % t rec(rst) t w(rst) reset ion after reset, i/os reconfigured as inputs start t rst ack or read cycle
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 15 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset fig 15. expanded view of read input port register fig 16. expanded view of write to output port register scl 002aae641 21 0 ap 70 % 30 % sda input 50 % int t v(int) t rst(int) t h(d) t su(d) scl 002aad735 21 0 ap 70 % sda output 50 % t v(q)
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 16 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 11. test information r l = load resistor. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 17. test circuitry for switching times fig 18. test circuit table 11. test data test load switch r l c l t v(q) 500 w 50 pf 2 v dd pulse generator v o c l 50 pf r l 500 w 002aab393 r t v i v dd dut 6.0 v open v ss c l 50 pf 002aac226 r l 500 w from output under test 2v dd open gnd s1 r l 500 w
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 17 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 12. package outline fig 19. package outline sot552-1 (tssop10) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (2) z (1) q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.15 0.23 0.15 3.1 2.9 3.1 2.9 0.5 5.0 4.8 0.67 0.34 6 0 0.1 0.1 0.1 0.95 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.4 sot552-1 99-07-29 03-02-18 w m b p d z e 0.25 15 10 6 q a a 2 a 1 l p (a 3 ) detail x l h e e c v m a x a y 2.5 5 mm 0 scale tssop10: plastic thin shrink small outline package; 10 leads; body width 3 mm sot552-1 1.1 pin 1 index
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 18 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 13. handling information all input and output pins are protected against electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 14.3 wave soldering key characteristics in wave soldering are:
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 19 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities 14.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 20 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 12 and 13 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 20 . table 12. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 13. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 20 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 15. abbreviations msl: moisture sensitivity level fig 20. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 14. abbreviations acronym description acpi advanced con?guration and power interface cbt cross-bar technology cdm charged-device model cmos complementary metal-oxide semiconductor dut device under test esd electrostatic discharge fet field-effect transistor ff flip-flop gpio general purpose input/output hbm human body model i 2 c-bus inter-integrated circuit bus i/o input/output led light emitting diode lp low-pass mm machine model por power-on reset smbus system management bus
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 21 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 16. revision history table 15. revision history document id release date data sheet status change notice supersedes PCA9537_5 20090507 product data sheet - PCA9537_4 modi?cations: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? pin names changed from i/o0, i/o1, i/o2, i/o3 to io0, io1, io2, io3, respectively ? section 6.4 reset input , 1st sentence: changed symbol from t w to t w(rst) ? figure 5 wr ite to output por t register : changed symbol from t pv to t v(q) ? figure 8 read input por t register : C changed symbol from t ph to t h(d) C changed symbol from t ps to t su(d) C changed symbol from t iv to t v(int) C changed symbol from t ir to t rst(int) ? t ab le 8 limiting v alues : C parameter description for symbol v i/o changed from dc voltage on an i/o to voltage on an input/output pin C parameter description for symbol i ss changed from supply current to ground supply current C symbol/parameter changed from i i/o , dc output current on an i/o to i o(ion) , output current on pin ion ? t ab le 9 static char acter istics , sub-section supplies: C symbol/parameter changed from i stbl , standby current to i stbl , low-level standby current C symbol/parameter changed from i stbh , standby current to i stbh , high-level standby current ? t ab le 10 dynamic char acter istics , sub-section port timing: C symbol/parameter changed from t pv , output data valid to t v(q) , data output valid time C symbol/parameter changed from t ps , input data setup time to t su(d) , data input set-up time C symbol/parameter changed from t ph , input data hold time to t h(d) , data input hold time ? t ab le 10 dynamic char acter istics , sub-section interrupt timing: C symbol/parameter changed from t iv , interrupt valid to t v(int) , valid time on pin int C symbol/parameter changed from t ir , interrupt reset to t rst(int) , reset time on pin int ? t ab le 10 dynamic char acter istics , sub-section reset: C symbol changed from t w to t w(rst) C symbol changed from t rec to t rec(rst) C symbol/parameter changed from t reset , time to reset to t rst , reset time ? figure 14 de? nition of reset timing : C symbol changed from t w to t w(rst) C symbol changed from t rec to t rec(rst) C symbol changed from t reset to t rst ? figure 15 expanded vie w of read input por t register : C changed symbol from t ph to t h(d) C changed symbol from t ps to t su(d) C changed symbol from t iv to t v(int) C changed symbol from t ir to t rst(int)
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 22 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset modi?cations (continued): ? figure 16 expanded vie w of wr ite to output por t register : changed symbol from t pv to t v(q) ? (old) figure 18, test circuit split into figure 18 t est circuit and t ab le 11 t est data C symbol changed from t pv to t v(q) ? added soldering information ? added t ab le 14 ab bre viations PCA9537_4 20060921 product data sheet - PCA9537_3 PCA9537_3 (9397 750 14259) 20041129 product data sheet - PCA9537_2 PCA9537_2 (9397 750 14052) 20040930 objective data sheet - PCA9537_1 PCA9537_1 (9397 750 12894) 20040820 objective data sheet - - table 15. revision history continued document id release date data sheet status change notice supersedes
PCA9537_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 7 may 2009 23 of 24 nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 17.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 17.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 17.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors PCA9537 4-bit i 2 c-bus and smbus low power i/o port with interrupt and reset ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 7 may 2009 document identifier: PCA9537_5 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 functional description . . . . . . . . . . . . . . . . . . . 4 6.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2.1 command byte . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2.2 register 0 - input port register . . . . . . . . . . . . . 4 6.2.3 register 1 - output port register. . . . . . . . . . . . 5 6.2.4 register 2 - polarity inversion register . . . . . . . 5 6.2.5 register 3 - con?guration register . . . . . . . . . . 6 6.3 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.4 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.5 interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.6 i/o port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.7 bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 8 7 application design-in information . . . . . . . . . 10 7.1 minimizing i dd when the i/os are used to control leds . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 9 static characteristics. . . . . . . . . . . . . . . . . . . . 11 10 dynamic characteristics . . . . . . . . . . . . . . . . . 13 11 test information . . . . . . . . . . . . . . . . . . . . . . . . 16 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 13 handling information. . . . . . . . . . . . . . . . . . . . 18 14 soldering of smd packages . . . . . . . . . . . . . . 18 14.1 introduction to soldering . . . . . . . . . . . . . . . . . 18 14.2 wave and re?ow soldering . . . . . . . . . . . . . . . 18 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 14.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 23 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 17.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 17.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 18 contact information. . . . . . . . . . . . . . . . . . . . . 23 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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